1. Field of the Invention
The present invention relates to digital data communications systems and, in particular, to an elasticity buffer that accommodates frequency differences between the receive clock and the local transmit clock in a data terminal while permitting timing drift between terminal clocks and maintaining constant timing between data packets.
2. Discussion of the Prior Art
In an "asynchronous" data communications system, each data terminal within the system receives incoming data from a transmitting station based upon a "receive" clock which is recovered from the incoming signal. However, the receiving terminal relies upon an asynchronous "local" clock to retransmit the data recovered from the incoming signal. Network synchronization is maintained by utilizing an elasticity buffer to compensate for the phase and frequency differences between the recovered receive clock and the local transmit clock.
Asynchronous data terminals transmit a contiguous series, or packet, of data characters which are separated by start-stop code patterns. The use of a unique start code ("start delimiter") and a unique stop code ("end delimiter") allows a receiving terminal to identify the exact beginning and the exact end of each received data packet.
When data signals are being transmitted from one data terminal to another, the recovery timing of the receiving terminal must be the same as or very close to the transmission timing of the transmitting terminal in order to achieve reliable data packet propagation. If there is a timing difference between the transmitting terminal and the receiving terminal, then receiver data sampling will drift, causing eventual data sampling error at the limits of the data packets and, hence, system malfunctioning.
In addition, metastability problems can be created by the phase differential between a data terminal's recovered write (receive) clock and local read (transmit) clock. If the read and write clock speeds are high in comparison to the intrinsic speed of the terminal's logic circuits, then a metastable state between logic "1" and "0" can persist and be propagated to the transmitted data. An obvious solution to this problem is to build faster logic. Another solution is to create a chain of latches to allow the metastability to settle out; this solution, however, introduces undesirable delay into the system.
The Fiber Distributed Data Interface (FDDI) protocol is an ANSI (American National Standards Institute) data transmission standard which applies to a 100 MBit per second token ring network that utilizes an optical fiber transmission medium. The FDDI protocol is intended as a high performance interconnection among mainframe computers as well as among mainframes and their associated mass storage subsystems and other peripheral equipment.
To reduce jitter in any data signal in a transmission ring, each terminal on the ring must transmit with its own local clock ("jitter" is the short term variation of the transition edges of a digital signal from their ideal positions). According to the FDDI protocol, this local clock is allowed to have a maximum frequency variation of only .+-.50 PPM from the transmit clock frequency of other data terminals in the system at a transmission rate of 125 Mbits per second. Because the transmitted data are encoded according to a 4B/5B scheme, that is, 4 bits of data are encoded to create a 5 bit symbol, the 125 MBit per second FDDI transmission rate translates to a 100 MBit per second data rate.
To accommodate the maximum allowable .+-.50 PPM frequency variation between data terminals on an FDDI network, it is desirable that an elasticity buffer be utilized in each terminal. The recovered receive clock writes data into the elasticity buffer and the local transmit clock reads the data from the elasticity buffer in a sequential fashion for further transmission.
The design of a conventional elasticity buffer is very straightforward. Basically, an elasticity buffer is a cyclic buffer queue, that is, a series of sequentially accessed storage registers wherein access for a particular operation, i.e. write or read, returns or "wraps around" to the first register in the series after the last register in the series has been accessed for that operation. Write pointer logic, typically an incrementing counter, holds the address of the register currently accessed for a write operation. Similarly, read pointer logic holds the address of the register currently being accessed for a read operation. The elasticity buffer's write pointer starts writing received symbols into the storage registers of the elasticity buffer upon receiving a start delimiter symbol and stops writing symbols after an end delimiter symbol has been written. Similarly, the elasticity buffer's read pointer starts reading symbols from the storage registers upon receiving a read-start signal and stops reading symbols after reading an end delimiter symbol.
A major limitation of the conventional elasticity buffer design is its requirement that a time gap of at least one symbol or more exist between sequential data packets. That is, a conventional elasticity buffer cannot handle back-to-back data packets with no separation. Since there is no predetermined start area for the second and subsequent back-to-back data packets, both the write and the read pointer logic must "remember" their previous positions. Furthermore, a conventional elasticity buffer cannot function with a continuous stream of line state symbols which contains neither a start delimiter nor an end delimiter.
Thus, it would be highly desirable to have available an elasticity buffer design which provides for periodic resynchronization of its write and read pointers to permit timing drift between receiver and transmitter clocks.
It would also be desirable to have available an elasticity buffer design which adjusts the length of start-stop code patterns to maintain constant timing between data packets.